Advanced-node capacity deployment and import/export controls were key industry themes this week. After a three-year hiatus, TSMC decided to return to Longtan for new fab construction, with Phase III of the Longtan Science Park expansion prioritizing sub-1.4nm (A14) angstrom-era advanced processes. Initial plans call for three fabs with total investment estimated at more than TWD 1tn (approximately USD 31.4bn), with the first fab targeted for completion around 2030. On trade policy, South Koreas revised Public Notice on Trade of Strategic Items took effect on September 1, bringing high-performance AI chips and advanced semiconductor equipment under export controls. Chinas Ministry of Commerce also issued a preliminary anti-dumping ruling on Japanese DCS, imposing cash-deposit rates of 80.8%–99.2%. Domestically, CXMT is accelerating DRAM capacity expansion, with monthly capacity expected to reach 350,000 wafers by end-2026; TSMC disclosed 2nm/3nm expansion plans for the first time; Nvidia invested USD 5bn in Intel, reshaping the AI chip landscape; CanSemi launched its IPO; and NAURAs backlog exceeded RMB 85bn.
CXMT G5 Fifth-Generation DRAM Platform Enters Volume Production with 11.95nm Active-Area Half-Pitch, Bringing Domestic High-End Memory into Flagship Smartphones
On September 20, CXMT Corporation (CXMT) announced at the 2026 World Manufacturing Convention that its fifth-generation DRAM technology platform (G5) had entered volume production. The company also showcased new high-capacity LPDDR5X products based on the platform. Key highlights include:
- ●Process breakthrough: Using an innovative quadruple-patterning process, CXMT has scaled the DRAM array active-area half-pitch to 11.95nm, reaching the level of the industrys leading nodes currently in volume production.
- ●Product ramp: Two 24Gb LPDDR5X products based on the G5 platform have both entered volume production, delivering 50% higher per-die capacity than comparable previous-generation products and using 496-ball and 245-ball packages, respectively.
- ●End-device breakthrough: The nubia NaviX Ultra, the worlds first AI-agent smartphone to adopt the new memory products, was launched at the same time, marking the first entry of domestically produced high-end memory chips into the mainstream flagship smartphone supply chain.
- ●LPDDR6 debut: CXMT also publicly showcased its volume-produced LPDDR6 memory for the first time at the event, giving the company an early lead in the next-generation mobile-memory standard.
- ●Technology roadmap: The G5 platform is a major result of CXMTs generation-skipping R&D strategy. Following volume-production iterations from the first through fourth generations, G5 volume production puts Chinas domestic DRAM process technology among the global leaders in volume-production technology.
The development sits at the core of DRAM manufacturing, with the node breakthrough driving upgrades across the supply chain:
- ▲Upstream: DRAM manufacturing equipment (etching, lithography, thin-film deposition), silicon wafers, photoresists, specialty gases and other materials; demand for equipment used in DUV multiple patterning is increasing.
- ▼Midstream: DRAM wafer manufacturing on CXMTs G5 platform, covering high-end mobile memory such as LPDDR5X and LPDDR6 and creating a four-player global landscape alongside Samsung Electronics, SK hynix and Micron.
- ●Downstream: Flagship smartphones, AI-agent devices, servers and PCs; domestic memory is entering the high-end consumer-electronics supply chain.
The impact will transmit through the supply chain, with different implications for each segment:
- ■Upstream equipment and materials: G5 uses quadruple patterning, driving continued demand for advanced etching equipment, photoresists and photomasks while creating more qualification and adoption opportunities for domestic DRAM equipment.
- ■Midstream memory manufacturing: Chinas domestic DRAM process technology is moving from catch-up toward parity. The global memory market is shifting from three-player dominance toward four-way competition, potentially intensifying price competition in high-end memory while strengthening domestic supply-chain resilience.
- ■Downstream applications: Domestic high-end memory is entering flagship smartphone supply chains, diversifying handset makers memory sourcing, reducing dependence on overseas memory leaders and accelerating adoption of AI-agent devices.
- ■Domestic industry perspective: G5 pushes the limits of DUV and demonstrates the feasibility of achieving advanced process scaling through multiple patterning without EUV, providing a reference path for technology breakthroughs in other semiconductor fields.
- ■Customs perspective: Import and export volumes of high-end DRAM chips will continue to rise. HS classification, origin determination, eligibility for tax exemptions and port inspection efficiency are becoming key variables in the memory supply chain.
Quadruple Patterning
+50% vs. Prior Generation
Global Top Tier
Domestic Memory Enters Flagships
Demand for high-end, low-power memory is surging across AI-agent devices and flagship smartphones, with LPDDR5X/LPDDR6 becoming standard for next-generation mobile devices.
CXMTs G5 platform enters volume production with an 11.95nm active-area half-pitch, with 24Gb LPDDR5X ramping at scale and LPDDR6 making an early global debut.
Quadruple patterning drives demand for advanced etching equipment, photoresists and photomasks, while accelerating qualification of domestic DRAM equipment and materials; DUV multiple patterning becomes critical.
Chinas domestic DRAM is moving from catch-up toward parity as the global market shifts from three dominant suppliers to four major players. G5 demonstrates the feasibility of advanced scaling through DUV without EUV, while entry of domestic high-end memory into flagship smartphone supply chains marks a major milestone. Yield ramp and market-share gains remain key follow-up indicators.
Update 1 | BIWIN Storage to Invest RMB 4.5bn in Wafer-Level Advanced Packaging and Testing, Launching Phase III Project in Dongguan Songshan Lake
On September 21, BIWIN Storage Technology Co., Ltd. (BIWIN Storage) announced that the company and its controlled subsidiary GBCC plan to sign a Phase III cooperation agreement for a wafer-level advanced packaging and testing manufacturing project with the Dongguan Songshan Lake High-Tech Industrial Development Zone Administrative Committee. Key details include:
- ●Investment: Total project investment is approximately RMB 4.5bn, including RMB 4bn in fixed-asset investment covering buildings, structures and ancillary facilities, as well as equipment.
- ●Location: Dongguan Songshan Lake High-Tech Industrial Development Zone. The project will expand within the existing site and requires no additional land.
- ●Scope: Phase III of the wafer-level advanced packaging and testing manufacturing project, further expanding advanced packaging and testing capacity and strengthening memory-chip packaging and testing capabilities.
- ●Completion: Fixed-asset investment is expected to be completed by December 31, 2029.
- ●Approval: The project was approved on September 21 at the 23rd meeting of the companys fourth board of directors and falls within the boards approval authority.
The project sits in the advanced packaging and testing segment of the memory-chip supply chain:
- ▲Upstream: Wafer-level packaging equipment, packaging materials (substrates, bonding wires, epoxy molding compound) and test equipment.
- ▼Downstream: Memory chips (DRAM, NAND, embedded memory), AIoT devices, smartphones, servers and other applications.
- ■Advanced memory packaging and testing capacity continues to expand in step with domestic memory-wafer manufacturing, strengthening local supporting capabilities in packaging and testing.
- ■Wafer-level advanced packaging is a key technology for memory-chip miniaturization and higher integration density. Capacity expansion should strengthen domestic memory suppliers competitiveness in high-end products.
- ■Dongguan Songshan Lakes semiconductor cluster is becoming more complete, with greater concentration of packaging and testing capacity supporting development of upstream and downstream suppliers.
- ■Rising demand for advanced packaging and testing equipment and materials creates more qualification and adoption opportunities for domestic equipment and packaging-material suppliers.
Update 2 | TSMC to Raise Foundry Prices 3%–6% from January 2027, Led by Advanced Nodes; Order Visibility Extends to 2030
On September 24, DIGITIMES, citing supply-chain sources, reported that TSMC has decided to adjust wafer-out pricing beginning in January 2027. Key details include:
- ●Price increase: Overall increases are expected at approximately 3%–6%, with larger hikes for advanced nodes such as 2nm and 3nm. Mature and specialty processes will be priced individually based on product mix, capacity utilization and customer-specific conditions.
- ●Capacity: Utilization at 8-inch fabs exceeds 100%, while processes below 45nm are at full utilization, leaving overall capacity tight.
- ●Order visibility: Supply-chain sources said TSMCs order visibility now extends to 2030, reflecting sustained strength in AI-chip demand.
- ●U.S. fab pricing: TSMCs Arizona fabs continue to reflect higher manufacturing costs, with foundry pricing remaining elevated.
- ●Company response: TSMC has not commented on the market reports, emphasizing that its pricing strategy is subject to official company announcements.
This development sits at the foundry-pricing stage and affects cost transmission across the semiconductor supply chain:
- ▲Upstream: Wafer-fabrication equipment and material suppliers; tight capacity continues to support upstream demand.
- ▼Midstream: TSMC foundry pricing feeds directly into manufacturing costs for chip design companies.
- ●Downstream: AI chips, smartphones, PCs, servers and other end products; higher chip costs may be passed through to end-product prices.
- ■Repeated TSMC price increases reflect persistent tightness in advanced-node capacity, with strong AI-chip demand the key driver. Order visibility through 2030 points to a longer industry upcycle.
- ■Manufacturing costs for chip-design companies will rise, increasing procurement costs for major customers including Apple, Nvidia and AMD, with part of the increase potentially passed through to end-product pricing.
- ■Domestic foundries such as SMIC and Hua Hong Grace retain price competitiveness in mature nodes. TSMCs price increases could strengthen their pricing power and market share.
- ■Customs perspective: Higher foundry pricing raises chip import costs, increasing the importance of HS classification, customs valuation and eligibility for tax exemptions in determining landed costs.
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1
Hua Hong Grace FAB9B Secures RMB 2.536bn in Earmarked Funding Under CDBs New Policy-Based Financial Instrument
Event: On September 17, Wuxi National Hi-Tech District Venture Capital Holding Group Co., Ltd. (WNDVC) secured support from China Development Banks new policy-based financial instrument, with RMB 2.536bn earmarked for construction of Hua Hong Grace FAB9B (Wuxi Phase III). It is Wuxis first loan under the new policy-based financial instrument in 2026 and the largest single such loan in Jiangsu this year. Hua Hong Phase III is planned as a 12-inch specialty-process foundry line with monthly capacity of 55,000 wafers.
Position: 12-inch specialty-process wafer manufacturing focused on power devices, analog chips and embedded memory.
Impact: Policy-based financing strengthens funding support for major semiconductor projects and Hua Hong Phase III capacity construction. Continued expansion of 12-inch specialty-process capacity will accelerate domestic substitution in power devices and analog chips.
Sources: Wuxi Release; Sina Finance; Cailian Press; Guangdong Semiconductor Industry Association -
2
Leading Interconnect Semiconductor to Invest RMB 12bn in Advanced IC Substrate Base in Baoan, Shenzhen, Focusing on High-End FCBGA Substrates
Event: On September 19, Leading Interconnect Semiconductor Technology (Shenzhen) Co., Ltd. officially broke ground on an advanced IC substrate smart manufacturing base at its second campus in Baoan District, Shenzhen. The project plans total investment of at least RMB 12bn and covers approximately 15.72 hectares. Several modern plants will be built in two phases, focusing on IC substrate products including FCBGA for applications such as AI, high-performance computing and networking. Leading is one of the few domestic suppliers to have achieved volume production of high-end FCBGA substrates.
Position: Advanced semiconductor packaging substrates; FCBGA substrates are core packaging materials for AI and high-performance computing chips.
Impact: Domestic high-end FCBGA substrate capacity continues to expand, helping close Chinas supply gap in advanced packaging substrates. Surging demand from AI compute hardware is accelerating Shenzhens semiconductor cluster toward higher-end capabilities.
Sources: Baoan District Government of Shenzhen; TrendForce; Tencent News; 10jqka -
3
GalaxyCore to Invest RMB 6.132bn in 12-Inch CIS Expansion in Shanghai Lingang, Adding 10,000 Wafers per Month
Event: On September 21, TrendForce reported that GalaxyCore Inc.s Shanghai semiconductor subsidiary plans total investment of RMB 6.132bn in a 12-inch CIS specialty-process capacity expansion project, including RMB 3bn in proceeds from fundraising. The three-year project will be located in the Shanghai Lingang Industrial Zone and will build on GalaxyCores existing 12-inch CIS R&D and wafer-manufacturing platform, adding monthly production capacity of 10,000 CIS wafers.
Position: 12-inch CIS image-sensor wafer manufacturing using specialty processes.
Impact: Domestic CIS capacity continues to expand, strengthening GalaxyCores in-house 12-inch wafer-manufacturing capabilities. Domestic substitution in CIS is accelerating, increasing image-sensor supply for smartphones, automotive electronics and security applications.
Sources: TrendForce; Sina Finance; GalaxyCore announcement -
4
BOE Completes End-to-End Commissioning of Glass-Core Packaging Substrate Pilot Line, Plans to Finalize Mass-Production Line Investment Within One Year
Event: On September 22, Chen Yanshun, Chairman of BOE Technology Group Co., Ltd. (BOE), said the company plans to finalize investment in a mass-production line for glass-core packaging substrates within the next year. BOE recently told institutional investors that its pilot line has completed end-to-end commissioning. At the same time, Intel is evaluating cooperation with display-panel maker AUO Corporation (AUO) on advanced packaging technologies centered on Micro LED and glass substrates.
Position: Advanced semiconductor packaging materials; glass substrates are emerging as a core material for next-generation advanced packaging.
Impact: Progress in glass-core packaging substrates marks a breakthrough as domestic display-panel manufacturers move into advanced semiconductor packaging materials. Glass substrates could overcome performance bottlenecks of traditional organic substrates and offer a new packaging option for AI chips.
Sources: Cailian Press; STAR Market Daily; JW Insights -
5
CanSemi Opens IPO Subscriptions on September 24, Set to Become Greater Bay Areas First Listed 12-Inch Specialty-Process Foundry on ChiNext
Event: On September 24, CanSemi Technology Inc. formally opened institutional and online subscriptions for its ChiNext IPO, offering 513mn shares before the over-allotment option. Preliminary price inquiry was completed on September 18. CanSemi is the first company in Guangdong to achieve volume production on 12-inch wafers. It currently operates two 12-inch fabs with combined planned monthly capacity of 80,000 wafers; after Phase IV is completed, total monthly capacity is expected to rise to 120,000 wafers, focusing on specialty processes for analog chips, power devices and related products.
Position: 12-inch analog and specialty-process wafer manufacturing; a core semiconductor manufacturer in the Greater Bay Area.
Impact: The Greater Bay Area semiconductor manufacturing sector is set to gain its first listed 12-inch foundry. Specialty-process capacity continues to expand, accelerating domestic substitution in analog chips and power devices and strengthening semiconductor supply-chain support across the Pearl River Delta.
Sources: CanSemi offering announcement; Securities Times; Shanghai Securities News
Chart 1 · Process-Node Comparison of Major Global DRAM Manufacturers (2026)
Chart 2 · Major Domestic Semiconductor Investment Projects This Week (Sept. 19–24)
Note: All figures are subject to official disclosures by the respective sources. In the event of any discrepancy involving qualifications or compliance information, announcements by the competent authorities shall prevail.
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