According to South Korea’s JoongAng Ilbo and other media outlets, citing anonymous sources from the ruling party, South Korea had originally planned to announce its first strategic investment project in the United States by the end of August. However, the negotiations have encountered new uncertainties, with reports suggesting that Washington wants South Korea to include investment in memory chip fabs among its U.S. investment options. On July 9, U.S. Commerce Secretary Howard Lutnick publicly named Samsung Electronics and SK Hynix, calling on the two memory giants to establish manufacturing operations in the United States.

According to the reports, South Korea had initially preferred an energy project as its first U.S. investment. However, sources cited by the media said new demands from the U.S. side had shifted the priorities of the negotiations. South Korea’s presidential office later clarified publicly that “reports that memory chips are being considered as the first strategic investment project in the United States are not true.” It nevertheless confirmed that South Korea and the United States are indeed holding investment consultations, without disclosing specific details of the negotiations.

Around the same time as the latest round of negotiations, Samsung Electronics and SK Hynix announced plans to invest more than KRW 800tn—approximately USD 565bn at prevailing market exchange rates—in expanding domestic memory production capacity in South Korea’s Honam region. Industry observers believe that if the two companies were also to undertake large-scale memory fab investments in the United States, they could face significant pressure on both capital and human resources. In addition, the memory industry has long investment payback periods and pronounced pricing cycles, while fab construction and operating costs are relatively high in the United States, creating practical challenges for commercial implementation.

Market analysts are concerned that amid the stalled bilateral negotiations, the U.S. could potentially raise tariffs on South Korean automobiles again, although Washington has not issued any formal notification to date. To advance the negotiations, South Korean Minister of Trade, Industry and Energy Kim Jung-kwan made an urgent visit to the United States in mid-August for consultations.

At the corporate level, Samsung Electronics and SK Hynix have only recently finalized massive capacity expansion plans in South Korea. Adding new memory production lines in the United States on top of these commitments would further stretch both capital and R&D talent. Combined with the high cost of building fabs in the U.S. and the pronounced cyclical volatility of the memory industry, the commercial viability of establishing large-scale memory production capacity in the United States faces substantial practical constraints.

The South Korean government therefore needs to strike a balance between safeguarding the foundations of its domestic memory industry, protecting the commercial interests of its companies, and addressing the negotiating demands of an allied country. The outcome of these negotiations could directly affect the global capacity strategies of Samsung Electronics and SK Hynix, while also potentially reshaping the regional structure of the global memory chip supply chain.

On August 18, Socionext announced that it will use Intel’s 18A-P process technology to develop custom SoCs targeting emerging demand from customers in data centers, edge computing, and high-performance computing. Socionext will combine its ASIC expertise with Intel Foundry’s advanced process and packaging roadmap to help customers develop differentiated SoC solutions optimized for specific application workloads. The first development project is reportedly a high-performance computing chiplet. Socionext is a leading Japanese SoC design company formed through the merger of the chip design operations of Fujitsu and Panasonic. It has deep technological expertise in areas including video and image processing, networking and communications, and high-performance computing.

From an industry trend perspective, Socionext’s order further validates the gradual evolution of the global advanced-node foundry market from a structure dominated by TSMC toward a more diversified supply landscape. Following the adoption of Intel’s 18A/14A processes by major customers including Microsoft, Nvidia, and AMD, the addition of Socionext, a leading Japanese ASIC company, adds an important Asia-Pacific component to the Intel Foundry ecosystem. For TSMC, customer diversification pressure is extending from major U.S. customers into the Asia-Pacific region. For Chinese chip design companies, the growing number of advanced-node foundry options could, over the medium to long term, provide a third alternative beyond TSMC and Samsung. However, the extent to which Intel 18A-P will be accessible to Chinese customers remains constrained by geopolitical factors.

On August 20, according to ETNews, industry sources said TSMC has successfully developed and validated backside power delivery technology for its advanced A16 process. A key aspect of the breakthrough is that A16 retains the gate density of N2P, the enhanced version of TSMC’s N2 process, as well as the design flexibility enabled by NanoFlex. According to the report, A16 moves the entire power delivery path to the backside of the chip and uses dedicated VB contacts to connect directly to the source and drain of the transistors. Under this architecture, TSMC needs to make only minimal adjustments to the gate structures, cell dimensions, and layout area on the front side of the chip, allowing A16 to maintain compatibility with existing chip designs. In terms of power efficiency, compared with N2P, A16 can deliver an 8%–10% increase in computing speed at the same power level. At the same performance level, power consumption can be reduced by 15%–20%, while chip density increases by 8%–10%. These characteristics make A16 particularly suitable for AI accelerators, high-performance computing, and other chips with demanding performance and power-efficiency requirements. A16 is expected to enter mass production in the fourth quarter of this year.

From an industry competition perspective, A16 is expected to enter mass production in the fourth quarter of 2026, progressing steadily in line with TSMC’s roadmap. Compared with Samsung’s 1.4nm (SF1.4) process, whose mass-production schedule has been pushed back to 2029, TSMC is further extending its timing advantage in advanced process technologies. The early commercialization of backside power delivery also means that, as AI chips impose increasingly stringent requirements on performance per watt, TSMC will be able to offer more competitive manufacturing options to core customers such as Nvidia and AMD. For China’s domestic foundry industry, TSMC’s dual lead in both process-node advancement and architectural innovation further raises the difficulty of catching up. It also reinforces the practical importance of pursuing differentiated breakthroughs in areas such as specialty mature-node processes and advanced packaging.

AMD recently unveiled its energy-efficiency outlook for rack-scale AI systems, highlighting a striking target: by 2030, just two next-generation AI racks could deliver computing performance equivalent to approximately 570 MI300X racks, while consuming only one-twentieth as much power during operation. In an official news release, AMD said AI compute energy efficiency had improved fourfold by mid-2026, exceeding its interim target of a threefold improvement and more than doubling the industry’s historical rate of progress. The company is steadily advancing toward its 2030 goal of achieving a 20-fold improvement in overall energy efficiency for rack-scale AI training and inference.

The target will be achieved through multiple technology pathways. AMD plans to use advanced process technologies to integrate more transistors into next-generation AI processors, bring HBM closer to the compute cores, enable real-time workload sharing between chips through high-speed UALink rack-scale interconnects, and optimize the software stack to reduce power wasted on unnecessary background computation. AMD has already launched its high-density Helios rack-scale platform, featuring Instinct MI455X GPUs, sixth-generation EPYC processors, Pensando AI NICs and DPUs, together with Infinity Fabric interconnect architecture and the ROCm software stack.

Notably, AMD places high-speed UALink interconnects, closer integration of HBM with compute cores, and advanced process technologies alongside one another as core technology pathways. This indicates that as transistor scaling slows, system-level architectural innovation is becoming a key driver of further energy-efficiency gains. The deployment of the Helios rack-scale platform has already provided a practical starting point for this roadmap. For the broader AI compute industry, as the tension between expanding compute capacity and rising power consumption becomes increasingly acute, whoever can first achieve an exponential reduction in power consumption per unit of compute will gain a decisive advantage in the next stage of competition.

On August 19, JCET Group announced significant progress in the R&D of advanced high-aspect-ratio TSV (Through-Silicon Via) technology and completed sample fabrication in collaboration with its partners. The sample fabrication focused on key processes including deep silicon etching, via-sidewall dielectric deposition, barrier and seed layer deposition, and copper filling. The fabricated TSVs have a diameter of 1.5 microns and a depth of 17 microns, achieving an aspect ratio of 11.3:1. JCET’s TSV fabrication solution targets high-end advanced packaging applications including 2.5D/3D advanced packaging, silicon-based interconnects, and multidimensional heterogeneous integration. The technology is intended to further strengthen the company’s core underlying process capabilities within its microsystem integration platform and provide more comprehensive and flexible one-stop manufacturing support for system-level integration of high-compute and high-memory chips. From an application perspective, JCET’s high-aspect-ratio TSV R&D capabilities can primarily support two high-end advanced packaging scenarios: 3D stacked integration and silicon interposers.

On August 19, Advanced Micro-Fabrication Equipment Inc. (AMEC) announced that its wholly owned subsidiary, AMEC Lingang, plans to invest in the Phase II project of the AMEC Lingang Industrialization Base in the Lingang New Area, with total planned investment of RMB 3.5bn, including RMB 1.7bn in fixed-asset investment. The project will focus on expanding production capacity for the company’s core product lines, including etching equipment, metrology and inspection equipment, and thin-film deposition equipment. Once fully ramped, the project is expected to generate annual sales revenue of RMB 3bn.

On the same day, AMEC released its 2026 interim report. Revenue reached RMB 6.691bn, up 34.89% YoY, while net profit attributable to shareholders of the listed company rose 300.22% YoY to RMB 2.825bn. Net profit excluding non-recurring gains and losses reached RMB 1.123bn, up 108.36% YoY. On the R&D front, the company invested RMB 2.041bn in research and development during the first half of the year, up 36.89% YoY, representing approximately 30.52% of revenue. Shipments of AMEC’s high-end products targeting critical etching processes in advanced logic and memory device manufacturing increased significantly, while multiple key etching processes for advanced logic and advanced memory devices have entered large-scale production. As of the end of June 2026, AMEC had developed 54 types of high-end semiconductor equipment, with more than 8,000 reaction chambers cumulatively deployed in mass production across over 220 production lines in China and overseas.

On August 19, Hwatsing Technology officially rolled out the first unit of its next-generation high-efficiency dual-table dicing system, the Versatile-DT300D, which has been shipped to a leading domestic advanced memory manufacturer. The equipment has been customized for applications including memory chips, advanced packaging, and image sensors. The Versatile-DT300D features an innovative fully automated dual-table dicing module integrated with a high-efficiency wafer handling system and an advanced high-purity cleaning system. While ensuring processing consistency, it significantly improves throughput per unit of time and delivers strong cleaning performance. Its intelligent metrology module further expands the scope of dicing metrology and defect inspection, enabling more comprehensive wafer quality monitoring during the dicing process and helping customers reduce defect risks and improve yield. The equipment also integrates an intelligent control software system that supports full-process data traceability and intelligent analysis. It can seamlessly connect with smart manufacturing platforms on semiconductor production lines, helping fabs achieve precise yield control and greater data transparency while fully meeting the stringent wafer-processing requirements of advanced process technologies and advanced packaging.